1. Field of the Invention
The present invention relates to integrated circuit structures which address charge accumulation during manufacture.
2. Description of Related Art
In the manufacturing of integrated circuits, some processes utilize activated ions. For example, backend processes including metal etching, photoresist stripping, and deposition of inter-metal dielectrics, involve plasmas which induce charge on the structures in the die being treated. This charging of structures during manufacturing can be referred to as the antenna effect.
Antenna effect induced charges may damage structures in the device, including structures critical to device performance. For example, in memory devices, word lines or other relatively large conductive structures can suffer significant charge accumulation due to the antenna effect. Charge accumulation on the word lines can expose tunnel dielectrics used in flash memory devices, gate dielectrics, and inter-polysilicon dielectrics, to damage by the accumulated charge. Furthermore, charge storage structures utilized in dielectric charge storage cells can be particularly susceptible to this kind of damage.
One characteristic of the plasma induced charge is that it may be either positive or negative, and different types of damage can occur based on the type of induced charge.
One approach to preventing or reducing the antenna effect is described in U.S. Pat. No. 7,196,369, entitled PLASMA DAMAGE PROTECTION CIRCUIT FOR A SEMICONDUCTOR DEVICE; by Chou et al. See also, U.S. Pat. No. 7,317,633 entitled PROTECTION OF NROM DEVICES FROM CHARGE DAMAGE; by Lusky et al.
It has been reported that the plasma charging effect plays a critical role in SONOS charge-trapping devices. In most Flash memory products, either PN diode protection, or poly fuse protection is adopted. However, both methods have limitations. For the PN diode protection, the word line WL operation voltage is restricted to only reverse direction of diode and must be lower than the breakdown voltage. Moreover, the PN diode only provides protection after breakdown voltage, thus it cannot protect the medium-range voltages. For poly fuse protection, it is necessary to rupture the fuse before measurement. The fuse protection is only suitable for small test device, but not suitable for a product design. Besides, if the rupture bias is too large it may disturb the device as well.
Electro static discharge (ESD) circuits have been deployed at the probing pads in integrated circuits to prevent inflated external electric pulses that damage the devices. However, ESD circuits are often activated under relative highs voltage and cannot provide a medium-voltage protection.
Accordingly, it is desirable to provide a protection circuit for use in the manufacturing of integrated circuits that protects against charge damage. Furthermore, the protection circuit should not affect device operation after manufacturing.